Embodiments of the present invention relate to integrated circuit (IC) packaging technology and more particularly to stacked die packages.
Today's ICs are manufactured with increasingly higher performance, reduced costs, and increased miniaturization of components and devices. Many ICs such as processors, controllers, logic devices, memory devices and the like may be housed in a package including a substrate which supports a semiconductor die and which further has internal electrical connections to provide interconnections (i.e., power and data) to the die. The package includes external electrical connections to enable the package to be electrically connected to, for example, a socket that may be adapted on a circuit board such as a motherboard or the like.
Thus the package may be used to provide power to the semiconductor die within the package, as well as to enable transfer of data to and from the die. Furthermore, a package provides a manner to dissipate heat from the die so that the device (e.g., a processor) therein can operate at its peak performance. Furthermore, the package protects the die from environmental damage.
Some semiconductor packages include a mixed stack of active devices. Specifically, some packages include two active die (i.e., two different semiconductor devices) that are stacked, one on top of the other, e.g., using an interface layer such as an epoxy or the like. Typically, these stacked die are memory-based devices such as flash memories. While such stacking of multiple devices can improve density of a resulting semiconductor package, certain problems exist. First, the top die in such a package may have limited availability of interconnects for power and data, as all such interconnects are typically provided to the top die using wire bonds from a substrate of the package. Because of space considerations as more functionality appears in a semiconductor device, the ability to provide sufficient power and data interconnects with wire bonds becomes difficult.
In some packages, the bottom die of a mixed stack may include multiple vias in an effort to overcome this problem of limited interconnections. In such packages, vias through the first die provide interconnections that can be directly coupled to the top die, e.g., by solder bumps that couple the top and bottom die. However, such an implementation creates thermal stress on the bottom die, as these interconnections are used to provide, in part, power to the top die.
Without stacking of die, data interconnections between active die (i.e., in different packages) typically require long interlinks through conductive layers of a circuit board, such as a motherboard. These long interconnects increase inductance and can further cause electrical noise. Furthermore, the distance of such interconnects reduces communication speed between different semiconductor devices.